Researchers Explore FP64 Emulation on Fixed-Point Tensor Cores
Researchers are exploring ways to emulate 64-bit floating-point precision using fixed-point tensor core units, a method becoming increasingly common in modern hardware accelerators. This approach, while offering potential performance gains, also presents numerical challenges, particularly in practical applications like dense linear solvers on modern GPUs.
To achieve this, scientists split integer emulation of 64-bit floating-point numbers up to seven times for correctness in dense linear solvers. They also generate matrices with positive random entries skewed towards larger values to improve numerical stability. However, this approach reveals new issues, impacting both performance and accuracy. Emulating FP64 with INT8 tensor cores offers a pathway to leverage performance gains in modern hardware for high-precision applications. The extended numerical range of matrix entries affects both performance and accuracy in high-performance computing, making this a high-stakes research topic.
Researchers are actively investigating split integer emulation of 64-bit floating-point numbers on fixed-point tensor cores. This approach, while promising, also presents challenges that need to be overcome to ensure both performance and accuracy in high-performance computing applications.
